diff --git a/arch/arm/mach-tegra/board-paz00-power.c b/arch/arm/mach-tegra/board-paz00-power.c index 21d0988..d5563f7 100644 --- a/arch/arm/mach-tegra/board-paz00-power.c +++ b/arch/arm/mach-tegra/board-paz00-power.c @@ -127,12 +127,12 @@ static struct regulator_consumer_supply tps658621_soc_supply[] = { .consumer_supplies = tps658621_##_id##_supply, \ } -static struct regulator_init_data sm0_data = REGULATOR_INIT(sm0, 725, 1275, true); -static struct regulator_init_data sm1_data = REGULATOR_INIT(sm1, 725, 1125, true); +static struct regulator_init_data sm0_data = REGULATOR_INIT(sm0, 725, 1450, true); +static struct regulator_init_data sm1_data = REGULATOR_INIT(sm1, 725, 1500, true); static struct regulator_init_data sm2_data = REGULATOR_INIT(sm2, 3000, 3700, true); static struct regulator_init_data ldo0_data = REGULATOR_INIT(ldo0, 1250, 3300, false); static struct regulator_init_data ldo1_data = REGULATOR_INIT(ldo1, 725, 1100, true); -static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1275, false); +static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1500, false); static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300, true); static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 1800, true); static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 2850, true); diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c index cd537d6..933e202 100644 --- a/arch/arm/mach-tegra/cpu-tegra.c +++ b/arch/arm/mach-tegra/cpu-tegra.c @@ -55,44 +55,52 @@ struct tegra_cpufreq_table_data { int throttle_highest_index; }; -static struct cpufreq_frequency_table freq_table_750MHz[] = { - { 0, 216000 }, - { 1, 312000 }, - { 2, 456000 }, - { 3, 608000 }, - { 4, 750000 }, - { 5, CPUFREQ_TABLE_END }, -}; - -static struct cpufreq_frequency_table freq_table_1000GHz[] = { - { 0, 216000 }, - { 1, 312000 }, - { 2, 456000 }, - { 3, 608000 }, - { 4, 760000 }, - { 5, 816000 }, - { 6, 912000 }, +static struct cpufreq_frequency_table freq_table_1000MHz[] = { + { 0, 216000 }, + { 1, 312000 }, + { 2, 456000 }, + { 3, 608000 }, + { 4, 760000 }, + { 5, 816000 }, + { 6, 912000 }, { 7, 1000000 }, { 8, CPUFREQ_TABLE_END }, }; -static struct cpufreq_frequency_table freq_table_1200GHz[] = { - { 0, 216000 }, - { 1, 312000 }, - { 2, 456000 }, - { 3, 608000 }, - { 4, 760000 }, - { 5, 816000 }, - { 6, 912000 }, +static struct cpufreq_frequency_table freq_table_1200MHz[] = { + { 0, 216000 }, + { 1, 312000 }, + { 2, 456000 }, + { 3, 608000 }, + { 4, 760000 }, + { 5, 816000 }, + { 6, 912000 }, { 7, 1000000 }, { 8, 1200000 }, { 9, CPUFREQ_TABLE_END }, }; +static struct cpufreq_frequency_table freq_table_1456MHz[] = { + { 0, 216000 }, + { 1, 312000 }, + { 2, 456000 }, + { 3, 608000 }, + { 4, 760000 }, + { 5, 816000 }, + { 6, 912000 }, + { 7, 1000000 }, + { 8, 1200000 }, + { 9, 1248000 }, + { 10, 1352000 }, + { 11, 1404000 }, + { 12, 1456000 }, + { 13, CPUFREQ_TABLE_END }, +}; + static struct tegra_cpufreq_table_data cpufreq_tables[] = { - { freq_table_750MHz, 1, 4 }, - { freq_table_1000GHz, 2, 6 }, - { freq_table_1200GHz, 2, 7 }, + { freq_table_1000MHz, 1, 4 }, + { freq_table_1200MHz, 2, 6 }, + { freq_table_1456MHz, 2, 7 }, }; static struct cpufreq_frequency_table *freq_table; diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index d50b4d4..b41cf0f 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -19,7 +19,7 @@ #ifndef _TEGRA_DVFS_H_ #define _TEGRA_DVFS_H_ -#define MAX_DVFS_FREQS 16 +#define MAX_DVFS_FREQS 32 struct clk; struct dvfs_rail; diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index d20a7df..dbeb29e 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -1768,12 +1768,66 @@ static struct clk tegra_pll_u = { }; static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { + /* 1.456 GHz */ + { 12000000, 1456000000, 728, 6, 1, 12}, + { 13000000, 1456000000, 896, 8, 1, 12}, + { 19200000, 1456000000, 910, 12, 1, 8}, + { 26000000, 1456000000, 896, 16, 1, 12}, + + /* 1.404 GHz */ + { 12000000, 1404000000, 936, 8, 1, 12}, + { 13000000, 1404000000, 972, 9, 1, 12}, + { 19200000, 1404000000, 585, 8, 1, 8}, + { 26000000, 1404000000, 972, 18, 1, 12}, + + /* 1.352 GHz */ + { 12000000, 1352000000, 676, 6, 1, 12}, + { 13000000, 1352000000, 936, 9, 1, 12}, + { 19200000, 1352000000, 845, 12, 1, 8}, + { 26000000, 1352000000, 988, 19, 1, 12}, + + /* 1.248 GHz */ + { 12000000, 1248000000, 624, 6, 1, 12}, + { 13000000, 1248000000, 960, 10, 1, 12}, + { 19200000, 1248000000, 650, 10, 1, 8}, + { 26000000, 1248000000, 960, 20, 1, 12}, + /* 1.2 GHz */ { 12000000, 1200000000, 600, 6, 1, 12}, { 13000000, 1200000000, 923, 10, 1, 12}, { 19200000, 1200000000, 750, 12, 1, 8}, { 26000000, 1200000000, 600, 13, 1, 12}, + /* 1.170 GHz */ + { 12000000, 1170000000, 975, 10, 1, 12}, + { 13000000, 1170000000, 990, 11, 1, 12}, + { 19200000, 1170000000, 975, 16, 1, 8}, + { 26000000, 1170000000, 990, 22, 1, 12}, + + /* 1.144 GHz */ + { 12000000, 1144000000, 858, 9, 1, 12}, + { 13000000, 1144000000, 968, 11, 1, 12}, + { 19200000, 1144000000, 715, 12, 1, 8}, + { 26000000, 1144000000, 968, 22, 1, 12}, + + /* 1.092 GHz */ + { 12000000, 1092000000, 910, 10, 1, 12}, + { 13000000, 1092000000, 924, 11, 1, 12}, + { 19200000, 1092000000, 910, 16, 1, 8}, + { 26000000, 1092000000, 966, 23, 1, 12}, + + /* 1.040 GHz */ + { 12000000, 1040000000, 780, 9, 1, 12}, + { 13000000, 1040000000, 960, 12, 1, 12}, + { 19200000, 1040000000, 650, 18, 1, 8}, + { 26000000, 1040000000, 1000, 25, 1, 12}, + + /* 1.014 GHz */ + { 12000000, 1014000000, 845, 10, 1, 12}, + { 13000000, 1014000000, 936, 12, 1, 12}, + { 19200000, 1014000000, 845, 16, 1, 8}, + { 26000000, 1014000000, 975, 25, 1, 12}, + /* 1 GHz */ { 12000000, 1000000000, 1000, 12, 1, 12}, { 13000000, 1000000000, 1000, 13, 1, 12}, @@ -2015,7 +2069,7 @@ static struct clk tegra_clk_virtual_cpu = { .name = "cpu", .parent = &tegra_clk_cclk, .ops = &tegra_cpu_ops, - .max_rate = 1200000000, + .max_rate = 1456000000, .u.cpu = { .main = &tegra_pll_x, .backup = &tegra_pll_p, @@ -2364,9 +2418,9 @@ static struct tegra_sku_rate_limit sku_limits[] = { RATE_LIMIT("cclk", 750000000, 0x07, 0x10), RATE_LIMIT("pll_x", 750000000, 0x07, 0x10), - RATE_LIMIT("cpu", 1000000000, 0x04, 0x08, 0x0F), - RATE_LIMIT("cclk", 1000000000, 0x04, 0x08, 0x0F), - RATE_LIMIT("pll_x", 1000000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("cpu", 1456000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("cclk", 1456000000, 0x04, 0x08, 0x0F), + RATE_LIMIT("pll_x", 1456000000, 0x04, 0x08, 0x0F), RATE_LIMIT("cpu", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), RATE_LIMIT("cclk", 1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C), diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c index a8f968d..58f46a0 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -41,27 +41,27 @@ static bool tegra_dvfs_cpu_disabled = true; static const int core_millivolts[MAX_DVFS_FREQS] = {950, 1000, 1100, 1200, 1225, 1275, 1300}; static const int cpu_millivolts[MAX_DVFS_FREQS] = - {750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125}; + {750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125, 1150, 1200, 1225, 1275, 1300, 1350}; static const int cpu_speedo_max_millivolts[NUM_SPEED_LEVELS] = - { 1100, 1025, 1125 }; + { 1450, 1025, 1125 }; static const int core_speedo_max_millivolts[NUM_SPEED_LEVELS] = - { 1225, 1225, 1300 }; + { 1500, 1225, 1300 }; #define KHZ 1000 #define MHZ 1000000 static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", - .max_millivolts = 1100, + .max_millivolts = 1450, .min_millivolts = 750, .nominal_millivolts = 1100, }; static struct dvfs_rail tegra2_dvfs_rail_vdd_core = { .reg_id = "vdd_core", - .max_millivolts = 1275, + .max_millivolts = 1500, .min_millivolts = 950, .nominal_millivolts = 1200, .step = 150, /* step vdd_core by 150 mV to allow vdd_aon to follow */ @@ -69,7 +69,7 @@ static struct dvfs_rail tegra2_dvfs_rail_vdd_core = { static struct dvfs_rail tegra2_dvfs_rail_vdd_aon = { .reg_id = "vdd_aon", - .max_millivolts = 1275, + .max_millivolts = 1500, .min_millivolts = 950, .nominal_millivolts = 1200, #ifndef CONFIG_TEGRA_CORE_DVFS